[Eug-lug] Concurrency, (free lunch is over article)

[Bob Miller]

Mike Cherba wrote:

> Both/either.  For example; One way we use multiple cores in our Network
> security processor designs is to dedicate cores to providing a specific
> stage of the network stack.  This allows much less cache thrashing and
> more efficient usage than if all the cores were in an SMP session and
> being used as available for whichever network processing needed to be
> done.  We can repurpose cores as needed to balance capacity with demand.
> The effectiveness of this and various other approaches does admittedly
> rely heavily on the underlying hardware architecture.  Does each core
> have its own cache?  how are bus accesses prioritiezed in hardware?  is
> this a Load/Store architecture or and EIP implimentation?  Do any of the
> cores have independant RAM?  I guess the real questin is going to be how
> to best use whatever design Intel/AMD decide to sell us.

Okay, now I understand.  I had thought you were arguing for
task-specific CPUs.  The interesting question is, how do the CPUs
interface with memory.  Presumably on-chip caches get bigger, and the
off-chip memory buses get faster, but can they be scaled as well as
the CPUs on chip?

> I'd love to meet some of these people. ( well
> actually I'd like to meet lots of people as I'm still new here and need
> to get out more now that I'm working from home )

Welcome to telecommuting.  I've been here 3.5 years, working with
engineers in Silicon Valley, and making and keeping local tech
contacts is hard.

You might enjoy the CS colloquia at the UofO.  They're irregularly
scheduled technical talks about all kinds of topics.  Send mail
to Cheri Smith <cheri at cs.uoregon.edu> and ask to be put on the
colloquia mailing list.

-- 
Bob Miller                              K<bob>
kbobsoft software consulting
http://kbobsoft.com                     kbob at jogger-egg.com